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IMX8M_how to decode the LPDDR4 fail address?

Question asked by Alex Jiang on Jul 25, 2019
Latest reply on Jul 26, 2019 by igorpadykov

IMX8M_how to decode the LPDDR4 fail address?

Platform:  I.MX8M + 4Gb_2channel _32bit LPDDR4; 

 

Density per channel (Gb)1:

2

Number of Channels

2

Number of Chip Selects used2

1

Total DRAM density (Gb)

4

Number of ROW Addresses2

14

Number of COLUMN Addresses2

10

Number of BANK addresses2

3

Number of BANKS2

8

Bus Width

32

 

addrmap register config:

0x0000001F

#DDRC_ADDRMAP0

0x00000000

#DDRC_ADDRMAP3

0x00001F1F

#DDRC_ADDRMAP4

0x00080808

#DDRC_ADDRMAP1

0x07070707

#DDRC_ADDRMAP5

0x0F0F0707

#DDRC_ADDRMAP6

 

refer to the addrmap register config, we decode LPDDR4 bank,row,column address as below:

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

  

  

  

  

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

R0

B2

B1

B0

C9

C8

C7

C6

C5

C4

C3

C2

-

-

 

but use the address decode excel(as above),the fail bank, row , clumn mismatch with the real failure addres of LPDDR4;

eg:

1. if we use the address decode excel(as above), we don't know bit27 & bit28 mean?

t1: memcpy SSN armv8_x32 test

.Address of test1 failure: 0x0000000053831748

Data was:                 0xFFFFFEFF00000200

But pattern was:          0xFFFFFFFF00000200

 

Fai address 0x53831748 – 0x40000000base =  0x13831748 = 0001 0011 1000 0011 0001 0111 0100 1000 , 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

  

  

  

  

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

R0

B2

B1

B0

C9

C8

C7

C6

C5

C4

C3

C2

C1

C0

0

0

0

1

0

0

1

1

1

0

0

0

0

0

1

1

0

0

0

1

0

1

1

1

0

1

0

0

1

0

0

0

 

2. If our decoder map is wrong? could you provide the right decoder map;

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