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Why are CS for SPI defined as GPIOs in Device Tree i.MX6

Question asked by Nemanja Savic on Jul 25, 2019
Latest reply on Aug 9, 2019 by gusarambula

I am reading at the moment the device tree documentation about SPI bindings while dealing with a custom board based on i.MX6DL (and Sabe Auto board). I have the following question, ECSPI controllers already have dedicated pins which can be configured as SS pins. Why do we define them in cs-gpios field and why are they configured as GPIOS. Here is an example from sabre auto board device tree:

 

&ecspi1 {
    fsl,spi-num-chipselects = <1>;
    cs-gpios = <&gpio3 19 0>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
    status = "disabled"; /* pin conflict with WEIM NOR */

    flash: m25p80@0 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "st,m25p32";
        spi-max-frequency = <20000000>;
        reg = <0>;
    };
};

 

And down is pinctrl entry:

        pinctrl_ecspi1: ecspi1grp {
            fsl,pins = <
                MX6QDL_PAD_EIM_D17__ECSPI1_MISO        0x100b1
                MX6QDL_PAD_EIM_D18__ECSPI1_MOSI        0x100b1
                MX6QDL_PAD_EIM_D16__ECSPI1_SCLK        0x100b1
            >;
        };

        pinctrl_ecspi1_cs: ecspi1cs {
            fsl,pins = <
                MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
            >;
        };

Shouldn't ECSPI controller automatically control SS its dedicated pin whenever an action on some device is initiated? So, why we don't choose SS option for that pin inside pinctrl but the GPIO?

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