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DDR drive strength and ODT udpate

Question asked by saravana kumar on Jul 23, 2019
Latest reply on Jul 23, 2019 by igorpadykov

val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, 0x00000200)

 

 

is it mandatory to set this register value in DDR3 image_header.s file... for setting the ODT on imx6 for data lines...

 

we are using imx6dp chipset and doing DDR3 calibration, in that we are including the ODT and drive strength,

 

MODULE imageheader
/*** Image Vector Table ***/
RECORD ivt
ivt_header: .word IVT_HEADER(IVT_VERSION)
entry: .word _start /* Absolute address of the IPL entry point */
reserved0: .word 0x0
dcd_ptr: .word dcd /* Absolute address of the device configuration data */
boot_data_ptr: .word bds /* Absolute address of the boot data */
self_ptr: .word ivt /* Absolute address of the image vector table */
csf: .word 0x0 /* Absolute address of the command sequence file, HAB */
reserved1: .word 0x0
END ivt;

/*** Boot Data Structure ***/
RECORD bds
/* i.MX6 use blocks on Boot Device for offset. */
boot_data: .word ivt - IVT_OFFSET

/* i.MX6 uses size of the boot image plus boot dev offset. */
image_len: .word _ecopy - ivt + IVT_OFFSET

/* No Plugin */
plugin: .word 0x0
END bds;

/*** Device Configuration Data ***/
RECORD dcd
dcd_header: .word DCD_HEADER(DCD_VERSION)

/****************************************************************************************************
* Setup DDR SDRAM pad configuration
***************************************************************************************************/

 

COMMAND write32
/* DDR3 IO Type */
val2addr(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, 0x000C0000)
val2addr(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)

/* DDR3 Clk Settings -- Differential, CMOS Hysteresis, ODT disabled, DSE changed from 48ohms to 60 Ohm */

val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, 0x00000020)
/* val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, 0x00000030) */

/* DDR3 Address Settings -- Differential, CMOS Hysteresis, ODT disabled, DSE changed from 48 to 60 ohms */
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B, 0x00000020)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B, 0x00000020)
val2addr(IOMUXC_SW_PAD_CTL_GRP_ADDDS, 0x00000020) /* DSE setting for A0 to A15 */
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B, 0x00000020)


val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, 0x00008000)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, 0x00008000)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, 0x00008000)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, 0x00008000)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, 0x00008000)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, 0x00008000)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, 0x00008000)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, 0x00008000)


/* DDR3 Control Settings */
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, 0x00000030)

val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, 0x00000020) /* Changed DSE from 48 ohms to 60 ohms */
/*val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, 0x00000030) */
val2addr(IOMUXC_SW_PAD_CTL_GRP_CTLDS, 0x00000020) /* Changed from 48 ohms to 60 ohms for CS0,CS1,SDBA2,SDCKE0:1,SDWE_B*/

/* Data strobe - Differential, CMOS Hysteresis, ODT changed from 40ohms to 60ohms, DSE changed from 48 Ohm to 60 ohms */

val2addr(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, 0x00020000)

val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, 0x00000220)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, 0x00000220)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, 0x00000220)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, 0x00000220)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, 0x00000220)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, 0x00000220)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, 0x00000220)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, 0x00000220)

/* CTL - set iMX6D DATA DRAM_DQ[31:0] ODT - changed from 40Ohm to 60ohms */

val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, 0x00000200)
val2addr(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, 0x00000200)


/* Data */

val2addr(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, 0x00020000)
/* set iMX6D DATA DRAM_DQ[31:0]Drive Strength DSE changed from 48ohms to 60ohm */

val2addr(IOMUXC_SW_PAD_CTL_GRP_B0DS, 0x00000020) /* Changed DSE from 40 ohms to 60 ohms for DATA00:07 */
val2addr(IOMUXC_SW_PAD_CTL_GRP_B1DS, 0x00000020) 
val2addr(IOMUXC_SW_PAD_CTL_GRP_B2DS, 0x00000020) 
val2addr(IOMUXC_SW_PAD_CTL_GRP_B3DS, 0x00000020) 
val2addr(IOMUXC_SW_PAD_CTL_GRP_B4DS, 0x00000020) 
val2addr(IOMUXC_SW_PAD_CTL_GRP_B5DS, 0x00000020) 
val2addr(IOMUXC_SW_PAD_CTL_GRP_B6DS, 0x00000020) 
val2addr(IOMUXC_SW_PAD_CTL_GRP_B7DS, 0x00000020) 


/* DATA, DDR3 DQM[7:0] Drive Strength changed from 48ohms to 60ohms , ODT =disabled */

val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, 0x00000020)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, 0x00000020)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, 0x00000020)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, 0x00000020)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, 0x00000020)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, 0x00000020)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, 0x00000020)
val2addr(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, 0x00000020)

END write32;

 

need suggestions on this.. is it mandatory to add the register value highlighted in red#..

Outcomes