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NXP 1052 and HyperRAM

Question asked by Michael Rooker on Jul 18, 2019
Latest reply on Jul 26, 2019 by Michael Rooker

I am currently using a 1052 core in a design in conjunction with an Altera Cyclone 5 FPGA. One of the things that take place in this design is that the ARM core using the smart memory controller accesses a piece of memory within the FPGA made to look like SRAM and transfers the data into SDRAM also attached to the ARM. The SRAM block is roughly 90K in size and I actually use the DMA to move the data on fixed intervals (every 4msec). The transfer speeds seem to be sluggish but acceptable for now but going forward that transfer rate requirement might drop to every 900usec. This leaves me with an issue because I can not move the data that fast currently. The hardware engineer and I are looking at other solutions and we stumbled on the ISSI IS66/67WVH8M8ALL/BLL 8Mx8 HyperRAM. We were thinking that by placing 2 on the board and ping ponging between them (the FPGA is filling one while I am reading the other) we would get the performance we need and then some. I was just wondering if anyone has any experience with these parts and this processor, are there any issues I should be aware of? Clearly the processor has the interface since it can execute in place from Cypress Hyperflash and since the controller is a dual unit I should be able to use the other channel for this. I have attached the PDF on this part if anyone is curious.

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