Wolfgang Wegner

Multiplexed FlexBus and non-shared SDRAM (MCF532x/7x)

Discussion created by Wolfgang Wegner on Feb 17, 2009
Latest reply on Feb 24, 2009 by Wolfgang Wegner

sorry if this is in fact obvious, but I would like to get this clarified before trying to test it myself in hardware...

When operating the devices (MCF532x/537x and probably most 52xx, too) in non-shared mode for (m)DDR, D15..D0 are mapped to D31..D16 internally. Is this a logical or a physical mapping, i.e. what happens to the multiplexed address bits? Is A31..A16 output in this mode, or A15..A0?

I see reasons for both possibilities, so maybe somebody who is using this configuration could comment on it.

Best regards,

PS: Just in case someone wonders about the pros for both variants: outputting A15..A0 would give the possibility to completely omit routing the address bus to more sophisticated slave devices, while outputting A31..A16 would extend the usable address range over the line A23 that is present in hardware.