When reading the user guide for M0+ (https://static.docs.arm.com/dui0662/a/DUI0662A_cortex_m0p_r0p0_dgug.pdf) on page 22 it says that SRAM starts at address 0x2000_0000. However, in the KL25 reference manual, the SRAM is divided in upper and lower sections, where the lower starts at 0x1FFF_F000 (for my 128 KB device). This would put it in the code section, according to the user guide.
I would just like to understand why this is the case? According to an answer to this question: Why is SRAM split, and what does it mean?, the M0+ does not have separate busses for upper and lower SRAM, so I don't really have to think about it. But even so, why go against the CPU memory model?
Edit: Corrected lower adress.