Download the bootloader project and the APP project to 274and debug the APP through the attach function.
The content of the test is , pause the two cores, and then view the data in the same SRAM region in the two cores. The results are as follows.
1、when the radar detected object
1)、view in Z4 core
2)、view in Z7_0 core
the data in the pictures above are the same.
2、when the radar detected no object
1)、view in Z4 core
2)、view in Z7 core
the data in the same address are different.
Conclusion:
from the point of view of the phenomenon, when there are bootloader project and APP project in the 274chip, when the radar does not detect the target, the data are different in the same SRAM region. In fact, it is only when the same SRAM region data is different between the two cores that the radar cannot detect the target (the Z7 core has target data after processing, but there is no such data in the Z4 core.Therefore, there is no target report after Z4 core processing).
Question: Why is it that viewing the same memory area in both cores results in different data? What caused it?
If anyone knows the reason, please tell me,thanks
Hi,
what about cache memory? Have you tried to disable cache memory or set the area as cache inhibited? SMPU can be used to set area as cache inhibited. You can reuse some code from:
Example MPC5748G SMPU initialization GHS614
or
Example MPC5748G SMPU initialization + Process ID test GHS614
Regards,
Lukas
