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Help with SGI interrupts on GICv2, imx6UL

Question asked by Vatsala Draviam on Jul 11, 2019

Hi,

 

I am trying to implement bare metal code on the imx6ul and I have tried to refactor code from imx6 SDK. The SDK provides CortexA9 implementation, but the processor I am working on is Cortex A7 with security extensions implemented and used.

 

Cortex A9 has GICv1. Cortex A7 has GICv2. I have refactored the code. Now I am trying to generate an SGI. The processor doesn't see the interrupt and hence processor state never changes.

 

I have checked that the processor is in SVC mode, in secure state, the interrupt handler is installed (I am able to test vector table by generating an abort exception), I and F bits in CPSR are cleared i.e. IRQ and FIQ are not masked.

 

In GICD_CTRL, Enable group0 and Enable Group 1 is set, IRQ is used to signal the processor.

In GICC_CTRL, EnableGrp0 and EnableGrp1 is set.

 

All interrupts are Group 0 and secure.

 

The interrupt priority level is 0xF8.

 

I am bit confused with the values to be written GICC_PMR register (priority mask level) and the priority of the interrupt itself.

 

The SDK code for A9 sets PMR to 0xff and BPR to 7, whilst the priority of SWI_3 (IRQ ID =3) is 0.

What value should I write to PMR and the priority of SGI? I tried setting PMR to 8 and priority of SGI to 16 (higher than the value in PMR) but it didn't work. The SDK values also don't work.

 

Earlier the value written to SGI was setting the target processor to a processor other than the processor that requested the SGI. As a result the PC jumped to the startup code, though processor state was still supervisor. I have changed this since imx6ul only has one core and I am not using virtualisation. So, now the code just loops waiting for an interrupt but the interrupt doesn't occur. What am I missing in the initialisation of interrupts with GICv2? I have attached the reset value of GICC registers.

 

Any pointers/help is greatly appreciated.

 

Thanks

Vatsala

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