MPC8349 Three-Speed Ethernet Controller (TSEC) has register DMACTRL[TDSEN, TBDSEN] and ATTR[RDSEN, RBDSEN] which control Rx/Tx/RxBD/TxBD data snoop enable. However, there is no description in the MPC8349 Ref. Manual Rev 1 about the behavior of these bits. I don't understand where the TSEC has a cache...
In my understanding, enabling DMACTRL[TDSEN] "Tx data snoop enable" enables the TSEC to look at transactions performed in DDR on the Tx buffers and ... what? invalidate it's Tx buffers internal cache if so?
In my system, I have enabled the core's data cache in copy-back mode on Rx and Tx descriptors and buffers. Is that correct or I should completely disable cache on the Rx/Tx buffers and RxBD/TxBD?
I am getting IEVENT[BSY] error... meaning that the TSEC sees all buffers as full.
Thanks for your help,