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i.MX6Q BT656 interlace capture problem.

Question asked by Takayuki Ishii on Jul 10, 2019
Latest reply on Oct 16, 2019 by ümit kayacık

Hello community,

 

I just try to capture bt656 interlace data.

Each register setting are same as 2.1.1 BT.656 Interlace Setting in document i.MX6 IPU TVIN Application Note.

 

IPU_CSI_SENS_CONF         0x04000A30
IPU_CSI_SENS_FRM_SIZE 0x020C02CF
IPU_CSI_ACT_FRM_SIZE   0x01DF02CF
IPU_CSI_OUT_FRM_CTRL  0x00000003
IPU_CSI_CCIR_CODE_1     0x010D07DF
IPU_CSI_CCIR_CODE_2     0x00040596
IPU_CSI_CCIR_CODE_3     0x00FF0000

 

In this time capture data will be swapped each odd/even field.

 

Line 0      Line 1

Line 1      Line 0

Line 2      Line 3

Line 3      Line 2

Line 4      Line 5

Line 5      Line 4

Line 6      Line 7

Line 7      Line 6

 

So, we try to change IPU_CSI_CCIR_CODE_1 and IPU_CSI_CCIR_CODE_2 to change F bit setting.

 

IPU_CSI_CCIR_CODE_1     0x00040596
IPU_CSI_CCIR_CODE_2     0x010D07DF

 

As a result, capture data is more differ as following.

 

Line 0      Line 1

Line 1      Line x

Line 2      Line 3

Line 3      Line 0

Line 4      Line 5

Line 5      Line 2

Line 6      Line 7

Line 7      Line 4

 

to capture these signals.

Which register does it modify to setup capture start line?

 

Best regards,

Ishii.

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