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How to rise the clock frequency in FRDM K64F to 96 MHz using the FLL in the MCG module?

Question asked by Alvaro Gutierrez Arce on Jul 10, 2019
Latest reply on Jul 14, 2019 by Mark Butcher


I am working with your FRDM K64F in bare metal. I read Chapter 25 (MCG) of the reference manual and I have managed to rise the clock frequency to 24 MHz using the FLL module by setting DMX32 bit in MCG_C4 register right after a system reset. However, when trying to rise the clock frequency by changing DRST_DRS bits in  MCG_C4 register to any other value different to 00, the program crashes. How can I achieve 96 MHz clock frequency shown in the table below? I am currently working within FEI mode, which is the default mode after a system reset.

MCG_C4 field description

Thank you in advance