According to UM10736:
15.7.7 Clearing the prescaler
When enabled by a non-zero PRE field in the Control register, the prescaler acts as a
clock divider for the counter, like a fractional part of the counter value. The prescaler is
cleared whenever the counter is cleared or loaded for any of the following reasons:
• Hardware reset
• Software writing to the counter register
• Software writing a 1 to the CLRCTR bit in the control register
• an event selected by a 1 in the counter limit register when BIDIR = 0
When BIDIR is 0, a limit event caused by an I/O signal can clear a non-zero prescaler.
However, a limit event caused by a Match only clears a non-zero prescaler in one special
case as described Section 15.7.8
When BIDIR is 0,there are only two conditions of event that clear a non-zero prescaler . Is it right?
1.A limit event caused by an I/O signal can clear a non-zero prescaler.
2. A Match only clears a non-zero prescaler in one special case as described Section 15.7.8,
I don't understand what 15.7.8 describe about the special case,and I don't want prescaler be cleared in my design.