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Question asked by pan liu on Jul 10, 2019
Latest reply on Feb 14, 2020 by Michael Stahl


I am trying to interface a SPI peripheral (slave) to my i.MX6 (master). 

According to the timing diagram requirements of this SPI peripheral, the i.MX6 needs to send a 16-bit command first, and then receive 16-bit data from the peripheral. During this period, the CS needs to be kept low. I set the burst length to 16. The CS will always be set high between the two bursts. 
How should I set the IMX6ul SPI to keep the CS signal line low between the two bursts? Now no matter what I try to set it, I can't achieve it, eg (SMC = 0, SS_CTL = 0, XCH = 1).