AnsweredAssumed Answered

Display on G133HAN01 LVDS using SN65dsi84 MIPI DSI LVDS bridge

Question asked by Antony Abee Prakash on Jul 8, 2019
Latest reply on Feb 9, 2020 by Srinu inaganti



We are using imx8m-ql custom board which has SN65DSI84 MIPI DSI LVDS bridge.

We are trying to bring up G133HAN01 LVDS panel display. We need to set the pixel clock between 134 MHZ to 145MHZ.


But the actual clock calculated is either 120Mhz (for pixelclock=134Mhz) or 150Mhz (for pixelclock=142Mhz).  We tried hard coding the actual_clk value with LVDS pixelclock(134 Mhz to  145 Mhz), but there is no impact.

Also we tried to change Video PLL clock from 594 to 424. But it is not at all changing. See the below error log


[ 0.803268] dcss-core 32e00000.dcss: Configured video pll 2 with ref_clk 1 freq 594000000 (actual 594000000)
[ 0.883445] imx-drm display-subsystem: bound imx-dcss-crtc.0 (ops dcss_crtc_ops)
[ 0.940146] dcss-core 32e00000.dcss: pixel clock set to 150000000 Hz instead of 141000000 Hz, error is 9000000 Hz


How can we configure dcss to operate at 424 MHZ ? so that we will get pixel clock of 141 MHZ for our LVDS panel.