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Restriction of Fractional Delay Circuit in KV5x to work

Question asked by Masato Nishimoto on Jul 4, 2019
Latest reply on Jul 9, 2019 by Alexis Andalon

Document KV5X sub-family reference manual describes 

   a) "The fractional delay logic can only be used when the IPBus clock is running at 100 MHz."

       in  FRAC_PU bit description of PWMx_SMnFRCTRL field.

   b) "Using the micro-edge placer block requires that the Fast-Peripheral clock be set within a
      valid frequency range (see the data sheet of this device for minimum and maximum
      values) and the core/system clock must be programmed to be 2x the Fast Peripheral
       clock." in 48.5.2.9.1 Fractional Delay Logic with Nano-Edge Placement Block

 

  For above b), data sheet indicates 120MHz as max value of Fast-Peripheral clock.

  If Fast-Peripheral clock is set to  120MHz, fractional delay logic will not work by reason a) ?

 Please help how I understand this conflict of restriction.

 BR.

 

    Masato Nishimoto

 

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