AnsweredAssumed Answered

DMA SPI and K20 PUSHR Register

Question asked by Greg Valvo on Jul 5, 2019
Latest reply on Jul 8, 2019 by Hui_Ma

Hi all. I have DMA-driven SPI transfers mostly working on the MK20DX256. There's only one issue that I can't resolve:

 

My observation is that 32-bit writes to the 'SPIx_PUSHR' register properly write the Control Word (upper half) and TXDATA (lower half).  However, subsequent 8 or 16-bit writes to PUSHR don't preserver the previous Control Word when they set the TXDATA field. Rather, it appears that these writes cause the Control Word to be set to 0x0000. Put another way, the Control Word is not "sticky".

 

First, is my observation correct? If so, it means that subsequent 8 or 16-bit DMA operations (after an initial 32-bit programmatic write) will result in 0x0000 for the Control Word.

 

This behavior causes 2 issues. The first is easy to handle, just make sure CTAR0 is properly set with your desired SPI configuration parameters. The second is that it's impossible to have the 'CONT' bit set in the control word for DMA transfers. This means that there is an unneeded Tdt delay added between every transfer, slowing down the whole process.

 

The only solution I've come up with so far is to make the DMA writes all 32 bits and include the desired Control Word in every one. But, this is horribly wastefull of memory as it requires the DMA buffer to be 2 X (16-bit SPI transactions) or 4 X (8-bit SPI transactions) larger than it needs to be.

 

So, anyone know if there's a way to make the PUSHR Control Word field "sticky".

 

Thanks in advance.

Outcomes