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MPC5674F EBI  External Generated D_TA  Timing Characteristics

Question asked by Steven Petrofsky on Jul 4, 2019
Latest reply on Jul 8, 2019 by David Tosenovjan

Configuration:      Using the MCP5674F power PC  EBI externaL 32 multiplexed bus mode and SETA=1

                                 for external D_TA;  the external peripheral supplies the /D_TA signal. to terminate the bus access



  1. Can D_TA externally generated transfer acknowledge go low for more than 1 clock period?
  2. What happens if the D_TA were to go low for 3 clock periods?  
  3. Would the cycle terminate on the D_TA going low or when it goes back High?