Configuration: Using the MCP5674F power PC EBI externaL 32 multiplexed bus mode and SETA=1
for external D_TA; the external peripheral supplies the /D_TA signal. to terminate the bus access
- Can D_TA externally generated transfer acknowledge go low for more than 1 clock period?
- What happens if the D_TA were to go low for 3 clock periods?
- Would the cycle terminate on the D_TA going low or when it goes back High?