What are the differences in the effect of Watchdog reset, POR, external reset signal, and SYSRESETREQ?

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What are the differences in the effect of Watchdog reset, POR, external reset signal, and SYSRESETREQ?

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atilla
Contributor II

I understand they are different reset sources, but is there any difference in what modules/peripherals they reset or not?

We do have an MK64FX board that uses i2s and DMA. Under some conditions (when the DMA IRQ handler is not fast enough to return before the next IRQ arrives) we get into a state where the watchdog timer might reset the system.

Here is what I have tried:

1. When the overflow is detected, run the function that initializes the i2s bus and DMA again. The audio data I read from now on is invalid, even after resetting the external audio chip as well.

2. When the overflow is detected, let the watchdog timer reset the chip. Similar to 1, the audio input is bogus.

3. Similar to 2, but during bootup if there is a watchdog reset, we also issue a soft reset request using SYSRESETREQ bit. The audio is still similar 1 and 2.

4. After 1, 2, or 3 happens, I generate an external reset signal by pressing a button. The whole hardware is re-initialized correctly.  Everything works again.

5. After a power-on, audio works without issues.

My question is, what might be happening that an external reset pulse can fix, but a watchdog or soft reset cannot?

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jingpan
NXP TechSupport
NXP TechSupport

Hi Atilla,

I can't find any difference between PIN reset and SYSRESETREQ on DMA and I2S. They should have same effect. Do you use I2S in and DMA to move data into SRAM? Does the error happened in I2S receive FIFO or DMA transfer data? What's the error data looks like?

Regards,

Jing

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