We write our own OS-agnostic drivers for the i.MX8QM display cores.
Are there any applications notes on how the PRG interacts with the GPU/dpu to resolve tiled buffers to linear for the display controller?
Some key points we are looking for:
- How does the buffer swap coordinate with v-sync to result in tear-free operation?
- Can the swapping on v-sync be coordinated without the use of interrupts? Some safety critical operating systems and clients prevent the use of interrupts.