Most processors have an RDY signal line to tell the bus to hold until I am done.
Configuration: A MPC5674F processor EBI external Multiplexed mode using chip select Access.
Problem: If a peripheral tied to a single /CS on that external bus needs requires an extra 2-3 wait states only part of the time, and "0" wait for states the majority of the time.
QUESTION: How do I tell the bus to extend add waits when the D_TA (bus acknowledge) signal is automatically internally generated.
- Can I override the D_TA to extend that bus access?
- Pull another line to inform the processor that the bus transfer is not complete and need more time?