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i.MX8M MIPI-DSI timing issue

Question asked by Giuseppe Pagano on Jun 29, 2019
Latest reply on Jul 9, 2019 by Giuseppe Pagano

Hi

we are facing an issue using MIPI-DSI interface from i.MX8MQ.

 

On our board a Full-HD LVDS display panel is connected to MIPI-DSI interface through a "MIPI-DSI to LVDS" bridge.

 

Most Full-HD displays work well in this setup, but in this project it is mandatory for us to use one Full-HD display panel that does not works correctly .... It is not possible to use another panel cause mechanical constraints.

 

                        

 

We discovered that the root cause for the missing syncronison on display was an unstable horizontal timelane lenght produced by MIPI_DSI from i.MX8M !!

 

In the following pictures I'm going to show the issue: first we transform LVDS digital signal in RGB signal, and acquire them with scope;

  YELLOW LINE = DATA ENABLE

   GREEN LINE = CLOCK

 

In this imagines you can see a not stable DE period ! In some acquisition it lasts 14.692 uSec in other acquisition 14.705 uSec. (N.B. It does not assume other values except this)

 

14.705 uSec

 

Further investigations showed that DE active period is always costant, but blank part of horizontal timeline sometimes miss a clock cycle (Fig below). This explains the reason why other Full-HD panel may work ...

 

Finally we found the root cause of the issue: MIPI-DSI controller of i.MX8M does not produce HSS packets with a constant period !!!!

To deeply analyze the ISSUE, we inspected MIPI-DSI LINE1 (differential signals). We plot a totally blank image on the screen to obtain a more clear mipi-dsi packets view.

 

Results are showed below:

                     

 

We realize that the MIPI-DSI controller spent a non constant time at the end of every HORIZONTAL TIMELINE, before starting with the new transmission

What is doing the controller in this fase ? Can we regolarize it ?

 

After a long session of tests we understand that this (variable) duration of that period is influenced by clock frequencies, and horizontal timeline lenght. But we cannot find how to manage it, nor searching in i.MX8M Reference Manual, nor by reversing engineer.

 

Can someone help us ?  We need to realize a working environment for this display for a very important project.

 

Here an explicative picture of DSI signal with a real image on the screen:

BLUE = Data Enable

GREEN = DSI LINE1

YELLOW = DSI Clock

 

 

 

Regards

Giuseppe

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