i.MX8M MIPI-DSI timing issue

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i.MX8M MIPI-DSI timing issue

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giuseppepagano1
Contributor III

Hi

we are facing an issue using MIPI-DSI interface from i.MX8MQ.

 

On our board a Full-HD LVDS display panel is connected to MIPI-DSI interface through a "MIPI-DSI to LVDS" bridge.

 

Most Full-HD displays work well in this setup, but in this project it is mandatory for us to use one Full-HD display panel that does not works correctly .... It is not possible to use another panel cause mechanical constraints.

 

                        WhatsApp Image 2019-06-29 at 12.36.52.jpeg

 

We discovered that the root cause for the missing synchronism on display was an unstable horizontal timelane length produced by MIPI_DSI from i.MX8M !!

 

In the following pictures I'm going to show the issue: first we transform LVDS digital signal in RGB signal, and acquire them with scope;

  YELLOW LINE = DATA ENABLE

   GREEN LINE = CLOCK

 

In this image you can see a not stable DE period ! In some acquisitions, it lasts 14.692 uSec in other acquisitions 14.705 uSec. (N.B. It does not assume other values except those)

 

scope_13.pngscope_12.png

 

Further investigations showed that DE active period is always constant, but the blank part of horizontal timeline sometimes misses a clock cycle (Fig below). For this reason other Full-HD panels could work ...

scope_17.png

 

Finally, we found the root cause of the issue: MIPI-DSI controller of i.MX8M does not produce HSS packets with a constant period !!!!

To deeply analyze the ISSUE, we inspected MIPI-DSI LINE1 (differential signals). We plot a totally blank image on the screen to obtain a more clear mipi-dsi packets view.

 

Results are shown below:

                     i.MX8MQ_DSI_L1-dataenable.png

 

We realize that the MIPI-DSI controller spent a non-constant time at the end of every HORIZONTAL TIMELINE, before starting with the new transmission

What does the controller in this phase? Can we regularize it?

 

After a long session of tests we understand that this (variable) duration of that period is influenced by clock frequencies and horizontal timeline length. But we cannot find how to manage it, nor searching in i.MX8M Reference Manual, nor with reversing engineer.

 

Can someone help us?  We need to realize a working environment for this display for a very important project.

 

Here is an explicative picture of DSI signal with a real image on the screen:

BLUE = Data Enable

GREEN = DSI LINE1

YELLOW = DSI Clock

 

C20_DEtime_2.png 

 

Regards

Giuseppe

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giuseppepagano1
Contributor III

Hi Igor, many thanks for the patch.

Currently we are using Linux and Android system with kernel 4.14.78 (and the patch fits very bad on that kernel), we understood the patch is for Linux kernel 4.14.98.

We patched a different Linux system with kernel 4.14.98, but unfortunately we achieved a strange behavior (DE active time becomes very short, about 4 uSec  ...).

We are currently investigating because we think there is something to be corrected on our dts file, after that we will verify if horizontal timeline became costant after the changes.

I'll update you in a couple of days.

Thanks for the help.

Regards

Giuseppe 

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rob_mclean
Contributor IV

I know it has been quite a few more than a couple days, but...

How did things turn out for you?

We are having problems with our MIPI display as well.  The symptom is different than yours, but I'm wondering if there is anything I can learn from your outcome?

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igorpadykov
NXP Employee
NXP Employee

Hi Giuseppe

one can try to improve timings with attached patches.

Best regards
igor
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westbrook
Contributor III

HI Igor,

Are these patches can be used for imx8mm?

I am now using imx8mm.

Thank you so much.

Best Regards,

Xiao

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