I have a couple of question regarding terminations required when routing ddr3 in fly by topology:
1) What resistor values are required for terminating address/command/control lines? I assume something close enough to single ended line impedance of 50 ohms. So will 47 ohms do the job?
2) What termination (with what resistor values) is required for the clock line. Hardware Guide recommends 2 series resistors Rn tied to a cap to VDD, which I assume is actually Vtt=VDD/2. Why is this type of termination required, as opposed to having the same techniques of each line individually up to Vtt thru a termination resistor.