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Lpspi slave transmission error with Yocto and i.mx8

Question asked by Erica Magari on Jun 26, 2019
Latest reply on Jun 26, 2019 by igorpadykov

Hello, I have a problem with my lpspi slave driver. I am using the i.mx8qmlpddr4arm2 board with Yocto Morty. I added lpspi slave support from newer kernel, in particular I am using this version of lpspi driver: https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/spi/spi-fsl-lpspi.c?h=imx_4.14.78_1.0.0_ga.

To make the system work correcty in my board I have modified the interrupt service routine of the driver:

 

static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
{
    u32 temp_SR, temp_IER;
    struct fsl_lpspi_data *fsl_lpspi = dev_id;

    temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
    fsl_lpspi_intctrl(fsl_lpspi, 0);
    temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);

    fsl_lpspi_read_rx_fifo(fsl_lpspi);

    if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
        fsl_lpspi_write_tx_fifo(fsl_lpspi);
        return IRQ_HANDLED;
    }

    if (temp_SR & SR_RDF && (temp_IER & IER_RDIE)) {
        complete(&fsl_lpspi->xfer_done);
        return IRQ_HANDLED;
    }

    return IRQ_NONE;
}

 

and the function write_tx_fifo:

 

static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
{
    u8 txfifo_cnt;
    u32 temp;

    txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;

    while (txfifo_cnt < fsl_lpspi->txfifosize) {
        if (!fsl_lpspi->remain)
            break;
        fsl_lpspi->tx(fsl_lpspi);
        txfifo_cnt++;
    }

    if (txfifo_cnt < fsl_lpspi->txfifosize) {
        if (!fsl_lpspi->is_slave) {
            temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
            temp &= ~TCR_CONTC;
            writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
        }
        fsl_lpspi_intctrl(fsl_lpspi, IER_RDIE);
    } else
        fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
}

 

My board in slave mode can comunicate with another board, and the data received is correct, but when I perform two consecutive transfers, the words received in the second one are read one word late, I mean it seems that the transmit fifo is not loaded in time so when a word arrives I am still loading the transmit fifo and the receive interrupt do not fire. It is weird because the data is sent one word each second, which is a lot of time. I have tried with clock speed at 100k hz, 200k hz and 500k hz.

What could be the reason of this behaviour? And how could I adjust it?

Thanks a lot,

Erica

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