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LS1021A:  D-cache does not work in u-boot environment

Question asked by Taizo Kojima on Jun 25, 2019
Latest reply on Jul 2, 2019 by Yiping Wang


We are developping control board using NSX LS1021A,
we have met d-cache problem.

We are now writing diag software as u-boot loadable programs,
since u-boot loadble modules can access fully hardware features.

Since we could not archive expected performance, we checked
program activity, and found I-cache is working, but D-cache is not.

We also checked using TWR-LS1021A-PB of freescale. The result is same.
Attached screen images are Lauterbach T32ARM's debug windows.

According to u-boot source code, u-boot enables I-cache and D-cache
using MMU. U-boot setups translation tables with long-descriptor
translation table format, normal memory, write-back write-allocate.

In image of TWRLS1021A-1.jpg, upper left window shows TLB,
upper right shows I-cache, middle right shows D-cache,
bottom center shows page table.

In image of TMWLS1021A-2.jpg,upper three windows show several registers,
bottom windows shows level-1 translation table. The table contains
4 long-descriptor entries.

1st: 0xbfff1003 00000000 # 1GB device memory and pcie ?
2nd: 0x40000411 00000000 # 1GB device memory
3rd: 0x8000041d 00000000 # 1GB normal memory, write-back, write-allocate
4th: 0xC000041d 00000000 # 1GB normal memory, write-back, write-allocate

In TLB window, 5th entry (idx=05) may be TLB of 3rd descriptor, because
of phisical address range mathing.
The logical adderss of the entry seems to be strange.
It should be C:80000000-BFFFFFFF, instead of 00000000--3FFFFFFF.
After boot linux, above problem disappear, and TLB and caches seem to be good.

When linux comes, I imagine some fixes may be done by OS code.

Is there any fixes or ERRATA, for enabling D-cache in u-boot
or for u-boot loadable modules

Best regards,

Taizo Kojima, Mitsubishi Electric Corp. Itami Works. Japan.

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