we are having a big issue in driving a Full-HD LVDS display on a custom board based on i.MX8MQ.
Display is connected to mipi-dsi bus through a MIPI-DSI to LVDS bridge from TI.
It was very difficult for us to find a working setup, because apparently MIPI-DSI controller of i.mx8mq produces a non regular data flow, so horizontal LVDS timeline from the bridge was not stable (this situation was acceptable from lots of display, but not from the display panel we was working on ..).
Finally we find the solution:
to mantain image syncronization on LVDS display we have to change "IMX8MQ_VIDEO_PLL1" frequencies from 599999999 to 600000000. We know this can't be the definitive configuration, but the question is: Why IMX8MQ_VIDEO_PLL1 was fixed to 599999999 values ? There is some limit on that clock, so it can't exceeded 60 MHz ?
Thanks for the help.