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S32R274 - PLL registers & configuration

Question asked by Riccardo Ertolupi on Jun 21, 2019
Latest reply on Jun 23, 2019 by Riccardo Ertolupi

Hello everybody,

 

I'm working on S32R274 and I want to set the PLL with the following setup:

  • Internal RC oscillator as the source for PLL0
  • The PLL0 as the source for system clock
  • PLL0 @ 160MHz setting prediv=2, mfd=40; rfd=2

 

To do that I should properly set the following registers:

  • MC_CGM_AC3_SC
  • PLLDIG_PLL0DV
  • ME_DRUN_MC

And then check ME_GS to see if the setup was activated.

 

My questions are:

  1. What is the base address of the PLLDIG module?
  2. Is my setup correct?

 

Thanks in advance for the help!

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