We are having a customized board with T1022 processor. We have connected FPGA on IFC bus with Chip select 1 of processor , and had done respective settings of GASIC mode in include/configs/T104xRDB.h file along with configuration for board/freescale/t104xrdb/law.c file. Both the files are attached .
When we are accessing the CPLD from u-boot , the u-boot generates an error suggesting to reset the board.
We have also tried to access CPLD in linux, there also the read command throws kernel panic exception.
When we are using logic analyzer inside our FPGA then our state machine is working fine returning the correct data and ready signal at desired time as shown in the GASIC timing diagram in Reference Manual.
When using GASIC write cycle, processor is not driving low on RW signal as observed from Logic Analyzer built inside FPGA.
I am attaching the both log of kernel and uboot crash along with T104xRDB.h (config file) and law.c (Local Access Window file).