I try to evaluate internal LDO of i.mx6QP.
In 52.7 PMU Memory Map/Register Definition of Reference manual IMX6DQPRM.
It have additional 3 registers for each PMU_REG_XXXX registers named _SET, _CLR and _TOG.
Does it funct that
- PMU_REG_xxxx : write 1 to set bit, write 0 to clear bit.
- PMU_REG_xxxx_SET : write 1 to set bit, write 0 is ignored.
- PMU_REG_xxxx_CLR : write 1 to clear bit, write 0 is ignored.
- PMU_REG_xxxx_TOG : write 1 to toggle bit(1->0 or 0->1), write 0 is ignored.
It have only one PMU_REG_xxxx register and
to read/write each register address are effect to PMU_REG_xxxx register.
Is it correct?