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i.MX RT1050: USB Host, SRI interrupt

Question asked by dongo on Jun 19, 2019
Latest reply on Jun 30, 2019 by Hui_Ma
  • Reference materials
    i.MX RT1050 Processor Reference Manual, Rev. 2, 11/2018

  • Question
    41.7.19 USB Status Register (USB_nUSBSTS), BIT7 SRI.
    There is the following description.

    In host mode, this bit will be set every 125 us and can be used by host controller as a time base.

    During USB High-Speed operation, is the SRI interrupt synonymous with the SOF packet transmission completion interrupt?
    Or is it a 125 us cycle interrupt that requests regardless of the SOF packet transmission timing?