Questions about SCLB in PCA 9517A

[masaru_tamai]

Hello.
We have placed a master on the A side of the PCA 9517 ADP and a slave on the B side.
Slaves are devices that perform clock stretching.
When SCLB is 0.5 V, when the slave performs clock stretching, does both drivers start and latch up?

[lisettelozano]

Hello Masaru Tamai,

First please accept my apologies for the delayed response.

Please note that for any arbitration or clock stretching it is required that the Low level on B side at the input of the PCA9517 needs to be 0.4V or below (VIL) in order to be recognized by the device and be transmitted to the A side.

I hope this can be helpful. Please let me know if you have further questions.

Have a great day, 

Paulina

[masaru_tamai]

Hello Paulina,

Thank you for your response.

When the slave is clock stretching, the voltage on B side has dropped to 0V. At this time, is the output driver to the B side disabled?
We are concerned about the bus conflict.

Best Regards,

[lisettelozano]

Hello,

It should not be disabled as per the value should be 0.4v or below (VIL and VILC in table 5) for clock stretching.

Have a great day,

Paulina