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RMII_SOLOX_EXTERNAL_CLOCK

Question asked by Victor Afanasiev on Jun 18, 2019
Latest reply on Jun 19, 2019 by Victor Afanasiev

I'm testing my board based on the processor i.MX 6SoloX. The 10/100/1000-Mbps Ethernet MAC CPU unit of the processor is used in the  RMII mode. Unfortunately, the Ethernet interface of my board doesn't work. The ENET1-REF_CLK1 signal uses an external 50 MHz reference clock that goes from the GPIO1-IO05 pin, rather than the ENET1-TX-CLK pin. The external reference clock has been checked by the oscillograph, the MII interface has been checked also. However, there is no connection with a host, the command ping gives out the following message:

=>Ping 10.0.01

Using FEC device

Ping failed; host 10.0.0.1 is not alive

 Please tell me, is it possible to use an external reference clock connected to the pin GPIO1_IO05 for working FEC in RMII mode, rather than ENET1_TX_CLK? If so, how I must set up the registers CCM_ANALOG_EENETn and IOMUXC_GPR_GPR1 for the RMII mode? Is it possible for the FEC to work in RMII mode with an external 50 MHz reference clock connected to the GPIO1_IO05 pin only? Should I use the ENET1_TX_CLK pin only for forking FEC in RMII mode with   the external reference clock? Is using of GPIO1_IO05 pin to form the REF_CLK signal the same as using of ENET1_TX_CLK pin? 

Is it enough to have only the external reference clock signal ENET1_REF_CLK1 of 50 MHz, connected to pin GPIO1_IO05 for working Ethernet MAC in RMII mode?  Do I need to configure the registers PLL_ENETn and ENET1_TX_CLK, if the frequency of the external clock signal is 50 MHz?

I am using the following setting in my_board.c file

static iomux_v3_cfg_t const fec1_pads[] = {

        MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),

        MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),

        MX6_PAD_GPIO1_IO05__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

        MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),

        MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

        MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

        MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

        MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

        MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

        MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),        

};

static int setup_fec(void)

{

        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;

        int reg, ret;

        unsigned char ethaddr[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }; 

 

        eth_env_set_enetaddr("ethaddr", ethaddr);             

/* Use 50MHz external clock */

        clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK, IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK);

       

        ret = enable_fec_anatop_clock(0, ENET_50MHZ);

        if (ret)

                       return ret;

       

        imx_iomux_v3_setup_multiple_pads(phy_control_pads,

                                                                       ARRAY_SIZE(phy_control_pads));

 

        /* Reset KSZ8463, active low */

        gpio_request(IMX_GPIO_NR(1, 13), "KSZ8463_rst");

        gpio_direction_output(IMX_GPIO_NR(1, 13) , 0);

        mdelay(10);

        gpio_set_value(IMX_GPIO_NR(1, 13), 1);

 

        /* Reset KSZ8081RNAIA PHY */

        gpio_request(IMX_GPIO_NR(5, 2), "KSZ8081_rst");

        gpio_direction_output(IMX_GPIO_NR(5, 2) , 0);

        mdelay(10);

        gpio_set_value(IMX_GPIO_NR(5, 2), 1);

       

        reg = readl(&anatop->pll_enet);

        reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;

        writel(reg, &anatop->pll_enet);

       

        return 0;

}

Outcomes