Hello everyone, i meet a emergence issue in our design. please, find someone to resolve this problem.
Look at 1050 user guide section SEMC controller, below the picture:
the MCR register bit[6] can change NOR/PSRAM RDY# polarity, BUT i can not find how to configure WAIT/RDY# pin. Because follow the IOCR register no bit to configure this function. That is very confused and mislead our design. Have someone can help me, thx.
Hi 钱汉望 钱 ,
Please check this table in chapter 24.4.3 Pin Mux in SEMC:
So, I think you can configure IOCR.MUX_RDY to 111, it is PSRAM address bit 27.
Wish it helps you!
If you still have question about it, please kindly let me know.
Have a great day,
Kerry
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