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Problem booting from internal flash in our hardware equipped with a NXP LPC54605

Question asked by Jakob Riis Employee on Jun 17, 2019

Hello NXP Support - I have a problem booting from internal flash in our hardware equipped with a NXP LPC54605.

What works: If I attach a J-Link debugger and program my .elf file into our hardware the software boots as expected. I have trace output on one of my uarts everything is fine. The J-Link debugger flashes the program into internal flash at location 0x0000000 and then jumps to the start of my code. Everything good.

What also works: On the NXP dev kit for LPC54618 I also have code running. My code programmed into internal flash at location 0x0000000 executes as soon as I power the dev-kit or press the reset button. In this board the ISP pins (PIO0_4, PIO0_5 and PIO0_6 are attached to buttons and they all have the value 1 which means that the MCU should boot from internal flash at address 0x00000000.

What does NOT work: On my hardware equipped NXP LPC54605 I cannot make the MCU execute code from internal flash at power-up or reset. Instead the MCU is executing code from the internal ROM (address area 0x03000000). On my NXP LPC54605 hardware I do not have access to the ISP pins. They are either not connected or connected to other peripherals. I have tried to follow to user manual UM10912 starting from Chapter 3: LPC546xx to get the image to boot using the ECRP bits and the enhanced image marker and boot block structure.

This what I have done. The first 8 vectors sums up to 0 as specified in section 3.3.2.7 (7 ISR vectors plus a sum calculated by the linker script). I have double checked that this is done correctly. At image address 0x24 I have the value 0xEDDC9494 (single enhanced image). At image address 0x28 I have the address of the boot block structure ( in my case this value is 0x124 as I have placed the boot block structure immediately after the vector table). At the boot block structure location I have the following parameters: 0xFEEDA5A5 // Header marker 0x00000001 // NO_CRC = 1 0x00000000 // Reserved 0x00000000 // Image length ( 0 because using no CRC) 0x00000000 // CRC value (0 because using no CRC) 0x00000000 // Version (0 because not using dual image I also have defined the ECRP value (address 0x20) to: #define ECRP ((2 << 10) | (1 << 12) | (1 << 14) | (2 << 16)) Which means (table 1022.ECRP controls): IAP Sector Erase/Write protection is disabled 01 Do not allow ISP entry via pins. 01 Do not allow ISP entry via IAP call SWD ENABLE Still I have no luck making the image boot on power up or reset. The device just cycles around on the ROM code (~ address 0x03003FB8) Question: Is it possible to boot from internal flash when ISP pins are not accessible or used for something else? How do I modify the image and ECRP values to make my image boot on reset and power up?

/Jakob

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