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i.MX8MQ LPDDR4 deep sleep mode

Question asked by Weide Ding on Jun 14, 2019
Latest reply on Jun 17, 2019 by Weide Ding


    I am debugging bottom current on my board, but find the 4GByte LPDDR4  is taking much current, around 70mA from NVCC_DRAM_1V1. Then I suspect my DDR4 does not enter deep sleep mode according to its specification.


There are below registers from DDR controller:

Low Power Control Register (PWRCTL)

Hardware Low Power Control Register (HWLPCTL)

Low Power Timing Register (PWRTMG)


I tried  them on uboot drivers/ddr/imx8m/lpddr4_init.c, but could not let DDR4 enter deep sleep mode after "echo mem > /sys/power/state" suspend in yocto.


Have NXP already implemented deep sleep mode? Where is the kernel code that i can try? Thanks a lot!


Wit Ding