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QN9080SIP-DK blocked

Question asked by Davide Ferrario on Jun 14, 2019
Latest reply on Jun 17, 2019 by Sebastian Delrio



I am working on a QN9080SIP based project.


I bought a QN9080SIP-DK board. I was able to compile/debug on the board.


After I configure hardware (I used MCUXpresso Config Tools) to enable external 32MHz clock and disable internal oscillator. The problem is that the generated code disable OSC32M before enable external clock.


After I upload the compiled code, I am no more able to access the board to download program/debug.


Is there some way I can solve this?




This is the MCUXpresso Config Tools generated code:


void BOARD_BootClockRUN(void)
    /*!< Power up/Power down the module. */
    POWER_EnablePD(kPDRUNCFG_PD_RCO32K);       /*!< Power down RCO32K */
    POWER_EnablePD(kPDRUNCFG_PD_OSC32M);       /*!< Power down OSC32M */

    /*!< Set up clock selectors - Attach clocks to the peripheries */
    CLOCK_AttachClk(k32M_to_XTAL_CLK);                  /*!< Switch XTAL_CLK to 32M */
    CLOCK_AttachClk(kXTAL32K_to_32K_CLK);                  /*!< Switch 32K_CLK to XTAL32K */
    CLOCK_AttachClk(kXTAL_to_SYS_CLK);                  /*!< Switch SYS_CLK to XTAL */
    CLOCK_AttachClk(kAPB_to_WDT_CLK);                  /*!< Switch WDT_CLK to APB */

    /*!< Set up dividers */
    CLOCK_SetClkDiv(kCLOCK_DivXtalClk, 0U);                  /*!< Set XTAL_DIV divider to value 1 */
    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 0U);                  /*!< Set AHB_DIV divider to value 1 */
    CLOCK_SetClkDiv(kCLOCK_DivFrg1, 0U);                  /*!< Set FRG_MULT1 to value 0, Set FRG_DIV1 to value 255 */
    CLOCK_SetClkDiv(kCLOCK_DivFrg0, 0U);                  /*!< Set FRG_MULT0 to value 0, Set FRG_DIV0 to value 255 */
    CLOCK_SetClkDiv(kCLOCK_DivApbClk, 0U);                  /*!< Set APB_DIV divider to value 1 */

    /*!< Enable/Disable clock out source and pins.*/

    /*!< Enable/Disable the specified peripheral clock.*/