I am trying to do ADC-self test for MPC5xxx family. When I enable ADC_0_STAW0R[WDTE] algorithm S timeout value. I am always seeing ADC_0_STSR1[WDTERR]. I have my ADC_0_STBRR[WDT] as 50ms.
1. Why is the ADC_0_STSR1[WDTERR] bit is set? Is there a sequence to enable ADC_0_STAW0R[WDTE]?
In the spec for ADC_0_STAW0R[WDTE] the description is as below.
Watchdog timer enable (related to the algorithm S).
Enables/disables the watchdog timer monitoring function for all ADC Supply self test steps.
The watchdog timer verifies:
• Correct sequence of the algorithm (step sequence)
• Execution of the algorithm within the safe time period as defined by STBRR[WDT]
As soon as the watchdog timer is enabled, execution must be detected within the safe time period. The
watchdog timer is reset each time the algorithm restarts.
This bit should be set only in scan mode.
2. what does it mean execution must be detected within safe time period?
Any help would be much appreciated.