Hi NXP Team,
We are developing a sensor just like KMA210, using S9KEAZN8AMFK as 24bit-SPI slave.
Time between SPI master CS low and CLK first rising clock is too short, about 4~5us.
I find out it takes about 2us from CS falling edge to software capture the edge using FTM capture(and GPO output high level in FTM interrupt function). If I write one data to SPI0_D after CS low, it may not have enough time to transmit the writing data and send out wrong byte order.
So, I write one byte data to SPI0_D register before CS low. But it results in another problem, that is, I can not refresh the SPI0_D after writing it except completing one byte transmitting. If I have write one byte to SPI0_D, it would be out of date in several minutes later.
How can I refresh KEA SPI data register(SPI0_D) for transmitting?