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Nexus3 Burst Read/Write access on MPC5566

Question asked by Rebecca Oostdyk on Jun 12, 2019
Latest reply on Jul 10, 2019 by Lukas Zadrapa

Hi all,

 

Thanks for taking the time to read my question. I'm attempting to create a JTAG programmer for an MPC5566 on the MPC5566 eval board. I've successfully connected to the 5566 through OnCE as outlined in AN3283. I can single step through instructions, and I'm ready to move on to loading the NXP-provided H7F SSD flash driver into the MPC5566's RAM. I am able to write a single RAM address through the Nexus interface and read it back to verify the write, but I can't perform a burst read or write. I think I'm missing a step in the documentation. Here's my basic process for the burst write:

1. Write the OCMD with the Nexus3 access instruction

2. Pass through the DR path of the OnCE TAP controller, shifting in the Nexus RWA code and indicating write access.

3. Pass through the DR path of the OnCE TAP controller, shifting in the RAM address to write to.

4. Pass through the DR path of the OnCE TAP controller, shifting in the Nexus RWCS code and indicating write access.

5. Pass through the DR path of the OnCE TAP controller, shifting in the configuration code for start access, write access, 64-bit, burst mode (0xD8200000).

6. Pass through the DR path of the OnCE TAP controller, shifting in the Nexus RWD code and indicating write access.

7. Pass through the DR path of the OnCE TAP controller, shifting in the bits to write to the memory specified in RWA.

 

The burst read process is almost identical except in step 6, RWD is specified for read access, and I shift out the bits into a variable in step 7.

 

I think the problem is step 7; the documentation doesn't specify how to shift in/out the bits using the TAP controller. The documentation only says that the data is latched from the Nexus register during a read when passing through the CAPTURE-DR state, and that data is shifted in during a write access when passing through the UPDATE-DR state. Should I shift in all the bits before I go through the UPDATE-DR state and then back to RUN-TEST-IDLE, or should I shift in 32 bits, or 64 bits, at a time, go through the UPDATE-DR, and then go back to SELECT-DR-SCAN for the next 32 or 64 bits? Or should I follow a completely different process? I've tried both the strategies outlined here, but I don't read back the correct values in RAM using my Nexus3 single access function after the burst write completes. Any clarification would be much appreciated.

 

Thanks!

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