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B4860 DDR init issue

Question asked by Luo Bob on Jun 11, 2019
Latest reply on Jun 30, 2019 by Luo Bob

Hello NXP freescale team;
    We are debuging b4860 u-boot(sdk-1.6) , we encount ddr init issue, we use 6GB ddr size,

4 GB for ddr10 controller, 2 ranks

2 GB for ddr1 controller, 1 ranks,

and the error log information as follows:

DDR: failed to read SPD from address 81
SPD error on controller 0! Trying fallback to raw timing calculation
Detected UDIMM RAW timing DDR
There is no rank on CS0 for controller 1.
Not enough bank(chip-select) for CS0+CS1 on controller 1, interleaving disabled!
Waiting for D_INIT timeout. Memory may not work.
2 GiB left unmapped

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