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Question asked by Paul Katarzis on Jun 10, 2019
Latest reply on Jun 11, 2019 by Paul Katarzis

I am working with a custom board that requires UART1_RTS_B to be used as a PWM output. I have currently configured our device tree to set the mux_mode of UART1_RTS_B to LSIO_PWM2_OUT. Our device tree is based on the following DTSI files from NXP: fsl-imx8qxp.dtsi, fsl-imx8dxp.dtsi, fsl-imx8dx.dtsi, and fsl-imx8-ca35.dtsi. I did not see any nodes in these files for the LSIO PWM modules and I did not see them enabled in the device tree for the IMX8QXP MEK. Therefore I have to write my own node for LSIO PWM 2. What I have written so far is based on the pwm_adma_lcdif, pwm_mipi_lvds0, and pwm_mipi_lvds1 nodes in fsl-imx8dx.dtsi:


pwm2: pwm@5d020000 {
compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
reg = <0x0 0x5d020000 0x0 0x10000>;
clocks = <&clk IMX8QXP_LSIO_PWM2_IPG_S_CLK>,
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QXP_LSIO_PWM2_CLK>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
power-domains = <&pd_lsio_pwm2>;
status = "okay";


I noticed that nodes such as pwm_adma_lcdif have the size cells of the reg property set to 0x0 0x1000, even though the memory map shows that region is 64KB. Should I also set the size cells of the reg property of my PWM node to 0x0 0x1000 even though the memory map says it is 64KB?


I found that dt-bindings/clock/imx8qxp-clock.h has the following clocks defined for LSIO PWM 2: IMX8QXP_LSIO_PWM2_DIV, IMX8QXP_LSIO_PWM2_IPG_S_CLK, IMX8QXP_LSIO_PWM2_IPG_SLV_CLK, IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK, IMX8QXP_LSIO_PWM2_HF_CLK, and IMX8QXP_LSIO_PWM2_CLK. I could not find an explanation for what these clocks do. What is the difference between the IPG_S, IPG_SLV, and IPG_MSTR clocks and which should be used for the IPG clock in my PWM node? Should the PER clock be set with the IMX8QXP_LSIO_PWM2_CLK or some other clock? Are the assigned-clocks and assigned-clock-rates properties set correctly in my PWM node?