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Fails to boot up device with 4GB LPDDR on iMX8QXP-B0 under eMMC boot mode, however uuu flashing is ok under serial mode

Question asked by Leon Uan on Jun 10, 2019
Latest reply on Jun 14, 2019 by igorpadykov



My customized images can be flashed into device via uuu tool, and its logs seems normal, see attached logs (uart log and uuu tool log). But device cannot bring up after changing boot switch to eMMC boot mode


Do you have any suggestion?


I pass DDR test using mx8_ddr_tool_ER8, and its ddr test logs
One-time test log: test_result_20190527-13'9'18.log
Overnight test log: test_result_20190531-9'7'37.log
DDR Test script: mx8qxb0_lpddr4_1200mhz_RPAv11_fs8700_1024Gb_MT53D1024M32D4.ds


Device boot up fail in emmc mode no matter ddr cfg file is generated based on v11 or v9 MX8QXP_LPDDR4_register_programming_aid excel file


I also tried the following settings, but device still fail to boot up
#changed size (memory@80000000) in uboot/linux dts to 2GB
#changed PHYS_SDRAM_2_SIZE to 2GB

My SCFW build cmd is:
make clean
make clean-qx
make qx B=mek R=B0 D=1 DL=5 M=0 Z=fs8700_1024Gb DDR_CON=ddr_stress_test_parser
mv build_mx8qx_b0/scfw_tcm.bin build_mx8qx_b0/scfw_tcm_fs8700_1024Gb_ddrtest


make clean
make clean-qx
make qx B=mek R=B0 D=1 DL=5 M=0 Z=fs8700_1024Gb
# "Z=fs8700_1024Gb" is my compile option for including MT53D1024M32D4 cfg file

Device info:
#Freescale i.MX8QXP revB A35 at 1200 MHz at 24C
#MT53D1024M32D4(Quad-Die, Dual-Channel, Dual-Rank Package)
#DDR cfg file is generated by MX8QXP_B0_LPDDR4_RegisterProgrammingAid_1.2GHz_v11.xlsx, and its basic settings are:
Memory type: LPDDR4
Manufacturer: Micron
Memory part number: MT53D1024M32D4
Density per channel per chip select (Gb)1: 8
Number of Channels (based on Bus Width)3 2
Number of Chip Selects used2 2
Total DRAM density (Gb) 32
Number of ROW Addresses2 16
Number of COLUMN Addresses2 10
Number of BANK addresses2 3
Number of BANKS2 8
Bus Width 32
Clock Cycle Freq (MHz) 1200
Clock Cycle Time (ns) 0.833333333