The IMX8QXPMEKHUG.pdf says
"The USB_SS3 and the USB_OTG2 are connected to the USB type C connector in the MEK board. The USB_OTG1 is connected to the USB OTG connector in the base board."
And there are wires between usb_otg2 pins from soc to typec socket in the imx8qxp-mek schematic.
However, I didn't find the USB_OTG2 description in the chip manual, especially for its base address. And u-boot and linux's dts nodes don't describe it.
My questions are:
Does the usb_otg2 exist on imx8qxp-mek? If yes, what is the base address?
Below is usb dts node excerpted from u-boot-imx/2018.03-r0/git/arch/arm/dts/fsl-imx8qxp.dtsi
==
usbmisc1: usbmisc@5b0d0200 {
#index-cells = <1>;
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x0 0x5b0d0200 0x0 0x200>;
};
usbphy1: usbphy@0x5b100000 {
compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
reg = <0x0 0x5b100000 0x0 0x200>;
clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>;
power-domains = <&pd_conn_usbotg0_phy>;
};
usbotg1: usb@5b0d0000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x0 0x5b0d0000 0x0 0x200>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>;
phy-clkgate-delay-us = <400>;
status = "disabled";
#stream-id-cells = <1>;
power-domains = <&pd_conn_usbotg0>;
};
usb2_phy: phy@0x5b160000 {
compatible = "fsl,imx8-usb-phy";
reg = <0x0 0x5b160000 0x0 0x10000>;
power-domains = <&pd_conn_usb2_phy>;
};
usb2: usb@0x5b110000 {
compatible = "fsl,imx8-usb3";
reg = <0x0 0x5b110000 0x0 0x38000>;
fsl,usbphy = <&usb2_phy>;
status = "disabled";
power-domains = <&pd_conn_usb2>;
};
