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i.MX8MM RMII reference clock

Question asked by Alexander Kudjashev on Jun 5, 2019
Latest reply on Jun 7, 2019 by Alexander Kudjashev

Hello, NXP team.

We have a custom board based on i.MX8MM, ethernet PHY LAN8720 with RMII connected as on imx8mm_val (TARGET_IMX8MM_DDR3L_VAL)


          pinctrl_fec1: fec1grp {
               fsl,pins = <
                    MX8MM_IOMUXC_ENET_MDC_ENET1_MDC          0x3
                    MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO     0x23
                    MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK     0x4000001f
                    MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1     0x56
                    MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0     0x56
                    MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1     0x56
                    MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0     0x56
                    MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER     0x56
                    MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x56
                    MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x56


RMII reference clock initialization is also similar to this board


static int setup_fec(void)
     struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
          = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
     * GPR1 bit 13:
     * 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also;
     * 0:enet1 rmii clock comes from external phy or osc

     return set_clk_enet(ENET_50MHZ);


but the reference clock 50 MHz on the pin MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK is missing.
I checked the integrity of the circuit by configuring this pin as a gpio output. Therefore, I have two questions:


1 Can anyone confirm that such clocking of the RMII works on i.MX8MM?
2 In which version of u-boot it is known that this clocking scheme works?