Jyothsna Rajan

Processor Master ID

Discussion created by Jyothsna Rajan on Jun 5, 2019
Latest reply on Jun 6, 2019 by Peter Vlna

Hi,

In the Reference Manual for MPC574x Power PC, interrupts section, there is frequent reference to Processor Master ID as in this description for the PSRn register configuration:

"

Only the processor with master ID zero will be allowed to write the INTC_PSRn[PRC_SEL,SWT]. When writing the INTC_PSR[PRI], only the processor with master ID 0 and the processor who’s master ID matches the setting of the
INTC_PSRn[PRC_SEL] will be allowed to write the INTC_PSRn[PRI]. An attempt by any other processor to write the PSRn[PRIn] will result in a termination error.
If INTC_MPROT[MPROT]=0 (disabled), all processors have write access.
If INTC_MPROT[MPROT]=1 (enabled), the processor with master ID (0-3) = INTC_MPROT[ID] or the corresponding processor has write access to INTC_PSRn[PRC_SEL,SWT], otherwise, a termination error is asserted. When writing
the INTC_PSRn[PRI], only the processor with master ID (0-3) = INTC_MPROT[ID] and the processor whose master ID (0-3) matches the setting of the INTC_PSRn[PRC_SEL] will be allowed to write the INTC_PSRn[PRI]. An attempt by any other processor to write the INTC_PSRn[PRI] will result in a termination error.

"

For all other configuration, I use the coreId of 0 to n-1 (n = number of cores) to split the processing between the cores. (a) What is master ID? is it different from coreId?  Is it configurable by the user?  

 

 

(b ) what does "corresponding processor" mean in the above description? 

 

(c) In S32DS, how can I configure MPROT and MPROT_ID using Processor Expert? 

 

(d) For my application, i want to use Software interrupt SS5_IRQn to interrupt core1 from core0. Only core0 should be able to set the interrupt and only core 1 should be able to clear the interrupt. How should the register be configured?

 

Thank you.

 

JoyR

 

@Alex_Peck

Brian Kreger

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