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s32k LPSPI RX FIFO clearing and NO Stall option

Question asked by Juan Hernandez on Jun 5, 2019
Latest reply on Jun 13, 2019 by Daniel Martynek


I have some questions regarding the use of LPSPI:

I am using S32K144 micro to communicate through SPI as a Master. 

I am observing that when the RxFIFO in LPSPI1_FSR-> RXCOUNT reaches the maximum (4), it makes the CS line to be held. I have the NO STALL option set to 0 for my LPSPI port, so I understand is actually STALLING the SPI.



If I debug, and have my debugger monitor the Register LPSPI1_FSR, when executing step by step, the RXCount is decremented on each step and alwas is either 1 or 0. However, when I use breakpoints to check why the SPI is not communicating I see that the register shows RXcount=4.


I am using only Transmit (TX) commands to write to another device through SPI. In most of the code I am using, I am not interested in reading the the info coming from the slave. i.e. I am triggering a watchdog trhough SPI, and I dont need to read the info in the RX line every time I trigger the watchdog. 

Q: Does this mean that I need to flush the RX FIFO every time I do a TX? What is the most efficient way to do that?

Reading the LPSPI1_RDR->DATA register?


If I choose not to use the STALL option, by setting NO STALL=1, I still see the RX FIFO gets full and if I try to read, Q: the information it will not be from the last command I sent but from the first, right? do I need to purge the RX FIFO before trying to do a request to read from my slave device?