We are experiencing a strange behaviour, that shouldn't be there according to the datasheet.
This is the situation: we have a device that acts as an SPI master.
This device is connected to an SPI port of our RT1051, and to the external QSPI flash via a resistor network.
In our idea, this should allow the Master to communicate with MCU under normal conditions, and to read/write the QSPI flash when the MCU is in reset.
In facts, I expect that all the pins of the MCU go in high impedance when the POR_B is deasserted.
When the MCU runs, everything goes fine.
When we set POR_B to zero, it seems that the MISO of the MCU is configured as an output at logic level zero. In facts, when the Master moves its MOSI, we read signals of circa 1 Volt of amplitude.
We also tried to completely disconnect the QSPI, and the issue is still there. So, apparently, the MCU does something strange that we don't understand.
The issue is still there if we set the MCU in permanent reset (POR_B to ground) and cycle power the board.
Specifically, we use LPSPI2 configured on pins E3 (sck), F3 (cs), F4 (miso) and G4 (mosi).
We have no level contention on pins E3 and F3, just on F4.