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How to reduce spikes on VDD when UART TX pin state changes?

Question asked by Florian PANTALEAO on Jun 4, 2019
Latest reply on Jun 12, 2019 by Florian PANTALEAO

Board: FRDM-K22F

Test project: hello_world from SDK demo_apps




We have noticed voltage spikes on our project board with Kinetis MK22FN256VLH12, they occur when UART0 TX pin state changes.

I have reproduced the problem when FRDM-K22F demo board and the simple hello_world project.

VDD supply is monitored with a scope trigged by UART1 TX pin state changes. TX pin is PORTE0 for hello_world project.

The spikes can reach 600 mV peak-to-peak with default project settings.

They can be reduced down to 60 mV peak-to-peak when the slew rate is configured to Slow with full pin configuration using PORT_SetPinConfig as shown in attached file.

60 mVpp is still too high if running ADC simultaneously.


Question: are there other settings (hardware and/or software) to further reduce these spikes?