hello, I can't find the reset value of the Peripheral Bridge (AIPS-Lite) about the register definition .
where could I find the AIPS chip-specific informations ?
Hi, it is stated in the first section of module description
Also about the AIPS(Peripheral Bridge), I am confused about the supervisor privilege level on AIPS_PACRn register.
Marked in red , is it means that if SPI is set，the master need supervisor access attribute and MPRx[MPLn] set ?
I know how to configure the MPRx[MPLn] bit , but how to configure the supervisor access attribute for the specified master?
If the particular master is the core, then its supervisor/user is given by MSR[PR]. Other masters are treated as supervisor.
Retrieving data ...