there is a problem understanding the ICS fully...
I want to use an MC9S08QG8 with a 16 MHz crystal, resulting in 8 MHz Bus clock. I need a fast running and accurately clocked application.
The MC9S08QG8 Data Sheet appears quite detailed but doesn't contain hints, which ICS mode is best suited for my needs. So I describe what I want to use and kindly ask for confirmation or improvements (or hints for the right literature).
The mode I would choose is "FLL Bypassed External (FBE)", but I cannot find any configuration with the "processor expert" software without any warning.
Essetially I cannot divide the external clock sufficiently (needed: /512, max. possible: /128) such that the FLL/filter input is in the range of 31.25 kHz to 39.0625 kHz.
I cannot find any statement, that the FLL must be feeded with such a low frequency. Ok, if I do not meet the condition, I cannot rely on DCOOUT and ICSLCLK. But does it do any harm, will any circuitry be damaged?
Can I use ICSC2=0x36 and, after waiting on OSC Initialization, ICSC1=0xb8?
All peripherals may be clocked with the BUS clock (8 MHz):
TPM, MTIM can be divided down sufficiently, ADC, IIC and SCI are said to work perfectly, BDM runs with 8 MHz - compatible with SpYder. The only question, provocated by warnings in the MC9S08QG8 Data Sheet and the "Processor Expert": What goes wrong when the range of 31.25 kHz to 39.0625 kHz for the FLL isn't met?
I would have appreciated some recommendations in the MC9S08QG8 Data Sheet, which ICS-mode is best suited for which needs; chapters 10.4.1.1 to 10.4.1.6 would be an ideal place for this - or does any other document exist which contains such information? An application note?
Thank you very much in advance for your help.
P.S.: I have searched...
Added p/n to subject.
Message Edited by NLFSJ on 2009-02-11 09:22 AM