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How to put MPC777C core in Halt or Reset

Question asked by petep Employee on May 30, 2019
Latest reply on May 30, 2019 by Peter Vlna

Hi,

Do we have any sample code which will put either of the MPC5777C cores into HALT or RESET?

My customer is trying to hold core 1 of the MPC5777C in reset but cannot get it to work.

 

From the reference manual, they should be able to do so.

According to the reference manual (8.2.41 Core1 Reset Vector Register), this should be possible.

 

8.2.41 Core1 Reset Vector Register (SIU_RSTVEC1)

This register contains the reset vector, reset control and instruction execution type selection for Core1. The RST bit is qualified by the CORE1 halt bit in the SIU_HLT1 register, such that both must be 1 for a core reset to occur. The order in which the RST and core halt bits are asserted does not matter. After both halt and RST bits are asserted, internal logic places a request to halt the corresponding core clocks, but the core may continue to run until such time that it terminates any pending crossbar master bus cycles and interrupt controller interaction that might prevent their use by other bus masters. When all pending transactions finish, the core will be in reset state with clock stopped.  Exit of reset state is done by negating either SIU_HLT1[CORE1] or the RST bit. Negating just one is enough to remove the core from reset state. Chapter 8 System Integration Unit (SIU, SIU_B) MPC5777C Reference Manual, Rev. 8, 11/2016 NXP Semiconductors 325 The reset value of the halt and RST bits for Core0 is 0 by default to allow Core0 to execute out of reset. The halt and RST bits for Core1 are 1 by default to prevent Core1 from executing out of reset. Any attempt to reset both cores by setting both RST bits will result in an immediate system reset, with the cause of the reset recorded in the SIU_RSR[CPURS] bit. NOTE The halt acknowledge bit in the SIU_HLTACK1 register will not be asserted for a core in reset state. Even though setting the halt bit is part of the procedure to put a core in reset state, the halt acknowledge bit is only asserted when the WAIT instruction is executed and the core is stopped, but not in reset state

 

If holding the device in reset is not possible, they could halt the core as well.  But they can't get this working either.

Any help would be appreciated.

Thanks,
Peter

 

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